1. Field of the Invention
The present invention relates to a semiconductor device producing method, and more particularly to a method of producing a CMOS (Complementary Metal Oxide Semiconductor) device.
2. Description of the Prior Art
Conventional CMOS device production involves the processes of well formation, element isolation region formation, N-channel transistor channel-stop implantation, N-channel transistor channel implantation, P-channel transistor channel implantation, gate electrode formation, LDD (Lightly Doped Drain) N.sup.- implantation, LDD P.sup.- implantation, source and drain N.sup.+ implantation, source and drain P.sup.+ implantation, contact hole formation, and metal wiring. Among those processes there are about twelve processes which require use of a mask.
FIGS. 1(a) to 1(f) show an example of such a conventional CMOS device production method, wherein step (d) in FIG. 1(a) is continued on step (e) in FIG. 1(e). The conventional method requires at least three masking or lithography processes before the gate electrode formation starts, as described below.
In more detail, a 60 nm thick silicon oxide film 52 and a 120 nm thick silicon nitride film 53 are formed on a surface of a silicon substrate 51 at step (a).
Then at step (b) a resist pattern 54 having an opening in an N-well formation region N is formed through photolithography, and the silicon nitride film 53 in the region N is removed. Subsequently, about 1.1.times.10.sup.13 cm.sup.-2 of phosphorus ions are implanted using the resist pattern 54 as a mask.
Then at step (c) the resist pattern 54 is removed and the substrate is subjected to an oxidization process to form a 390 nm thick oxide film 55 in the region N. At this time, an N-well 56 is formed in the substrate 51. After removing the remaining silicon nitride film 53, about 1.2.times.10.sup.13 cm.sup.-2 of boron ions are implanted. The ion implantation energy is so set that the ions do not pass through the oxide film 55, whereby the boron ions are implanted only in a silicon substrate region P which is not covered with the oxide film 55.
Then at step (d) the substrate is thermally treated to form a P-well 57 having a depth of 1.5 .mu.m.
According to this conventional method, the P-well 57 is formed without requiring a resist pattern formation step and using the oxide film as a mask, that is, the P-well is self-aligned. However, disadvantageously a difference in level of 0.17 .mu.m takes place at the boundary between the N-well and the P-well.
Then at step (e) an oxide film 58 and a silicon nitride film 59 are formed on the entire surface of the silicon substrate 51. Subsequently, using a second resist pattern (not shown) having an opening for each element isolation region 60, the silicon nitride film 59 in each element isolation region 60 is removed. In order to increase the concentration of boron in the P-well 57 underneath each element isolation region 60, a third resist pattern 61 is formed which has an opening in each element isolation region 60 of the P-well 57, and about 3.times.10.sup.12 cm.sup.-2 of boron ions are implanted from above the resist pattern 61.
The reason for the implantation of boron ions in the P-well is as follows. Boron ions constituting the P-well tend to be segregated from the P-well into an oxide film during the formation of the oxide film through heat-treatment. Therefore, when the element isolation regions are formed by a LOCOS method involving a heat-treatment after completion of the wells as in the conventional method described herein, boron ions in the P-well are segregated into the oxide layer of each element isolation region and the boron concentration decreases at a portion below the LOCOS oxide layer. This in turn causes a field inversion because positive electric charges exist at the interface between the oxide layer and silicon. In order to prevent this from occurring, in the conventional method, boron ions are preliminarily implanted in portions corresponding to the element isolation regions in only the P-well to compensate the decrease in the boron concentration during the heat treatment of the substrate.
For the above reason, an extra dosage of impurity was implanted only in the element isolation regions in the P-well. It is noted that the ion implantation energy is set to such a level that the boron ions do not pass through the silicon nitride film 59 in order to prevent the boron from entering into the active regions.
At step (f), after removing the resist pattern 61, the whole substrate is subjected to an oxidization process to form an oxide film 62 having a thickness of 0.4 .mu.m as isolator. At this time, a heavily boron-doped region 63 being a channel-stop layer is formed under each element isolation region in the P-well. Subsequently, the oxide film 5 is removed and an oxide film 64 is newly formed on the top surface of the substrate, and about 3.times.10.sup.12 cm.sup.-2 of boron ions are implanted for controlling the threshold voltage of transistors to be formed.
In the process of forming source and drain diffusion layers after the gate electrode formation, all the ion implantation processes are completed in at least two masking or lithography processes.
There is also proposed a seven mask CMOS process using a special oxide deposition method (K. Kanba et al., "A 7 Mask CMOS Technology Utilizing Liquid Phase Selective Oxide Deposition" EDM 91, treatise No. 25.1.)
As described above, the conventional method has an advantage that self-alignment can be used for the formation of the P-well. However, since the formation process of the element isolation regions involving a heat-treatment of the substrate follows completion of the wells, an additional ion-implantation process is required for formation of a channel-stop layer for the above-described reason. This additional ion-implantation requires an additional masking or lithography process.
The number of steps required for producing an LSI is approximately proportional to the number of masking processes. Increase in number of processes leads to the reduction of yield, which in turn results in increase of prices more than the natural increase of production costs due to the mere increase in number of processes.
If it is attempted to produce the channel-stop layer without using the masking process for defining the channel-stop region, each element isolation region in the P-well is required to have a significantly great width. Furthermore, since a difference in level takes place between the N-well region and the P-well region, a focus margin in an optical exposure process for pattern formation is reduced, which disadvantageously causes a constriction to take place in a pattern which intersects a stepped portion formed between the wells due to the difference in level. Furthermore, since the impurities are distributed in the substrate through diffusion in both the wells, it is impossible to achieve an accurate control of the distribution profile of impurities in the channel section of each transistor. Accordingly, it is impossible to take appropriate measures against the short channel effect of the transistor.